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7si21xx: %s: timeout!!
7si21xx: %s: readreg error (ret == %i)
7si21xx: %s: writereg error (reg1 == 0x%02x, data == 0x%02x, ret == %i)
7si21xx: %s: writereg error (reg == 0x%02x, data == 0x%02x, ret == %i)
7si21xx: %s: readreg error (reg == 0x%02x, ret == %i)
7si21xx: %s : AGCPWR: 0x%02x%02x, signal=0x%04x
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si21_readreg si21_writereg si21xx_release si21xx_init si21xx_sleep si21xx_set_symbolrate si21xx_setacquire si21xx_set_frontend si21_read_status si21_read_ber si21_read_signal_strength si21_read_snr si21_read_ucblocks si21_writeregs si21_readregs si21xx_send_diseqc_msg si21xx_wait_diseqc_idle si21xx_send_diseqc_burst si21xx_set_tone si21xx_set_voltage si21xx_attach debug ( ' E( $) *,-./04 5EFEGH I@JLO.P.QRVY Z-[3\ _vbcdey@j@k
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